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dg508a_mil/509a_mil vishay siliconix document number: 70067 s-00405erev. c, 21-feb-00 www.vishay.com faxback 408-970-5600 5-1 single 8-ch/differential 4-ch cmos analog multiplexers (obsolete for non-hermetic. use dg408/409 as pin-for-pin replacements.) low on-resistance: 240 ttl and cmos logic compatible low power: 30 mw break-before-make switching 44-v power supply rating transition time: 600 ns easily interfaced low power consumption low system crosstalk wide analog signal range communication systems ate data acquisition systems audio signal routing and multiplexing medical instrumentation the dg508a_mil, an 8-channel single-ended analog multiplexer, is designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (a 0 , a 1 , a 2 ). the dg509a_mil, a dual 4-channel analog multiplexer, is designed to connect one of four differential inputs to a common output as determined by its 2-bit binary address (a 0 , a 1 ) logic. break-before-make switching action protects against momentary shorting of the input signals. a channel in the on state conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails, normally 30 v peak-to-peak. an enable (en) function allows for device selection when several multiplexers are used all control inputs, address (a x ) and enable (en) are ttl or cmos compatible over the full specified operating temperature range. fabricated in the vishay siliconix plus-40 process, the absolute maximum voltage rating is extended to 44 v, allowing increased operating headroom for standard 15-v signal swings and operation with 20-v supplies. an epitaxial layer prevents latch up. the dg508a_mil/509a_mil are available in hermetic packages. for plastic packages, use the dg408/409 as pin-for-pin replacements. for applications requiring address data latching, the dg528/529 is recommended. dg408/409 is recommended for higher precision applications. for wideband/video routing and multiplexing, the dg538a is recommended.
s 3 a 0 s 6 d s 4 a 1 s 8 s 7 en dual-in-line a 2 v gnd s 1 v+ s 2 s 5 decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg508a_mil key v nc gnd s 8 s 1 s 7 v+ s 4 nc d nc nc s 2 a 1 s 5 a 2 s 3 en s 6 a 0 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 top view lcc decoders/drivers dg508a_mil
dg508a_mil/509a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-2 document number: 70067 s-00405erev. c, 21-feb-00

temp range package part number 0 to 70 c 16-pin plastic dip dg508acj 25 to 85 c 16-pin cerdip dg508abk 40 to 85 c 16-pin narrow soic dg508ady 55 125 c 16 - pin cerdip dg508aak 55 125 c 16 - pin cerdip dg508aak/883 55 125 c lcc-20 dg508aaz/883 55 125 c 16 - pin sidebraze 7705201ea 55 to 125 c 16 - pin sidebraze 7705201ec 16 - pin flat pack 7705201fa 16 - pin flat pack 7705201fc 16 - pin sidebraze jm38510/19007bea 16 - pin sidebraze jm38510/19007bec
a 2 a 1 a 0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 logic a0o = v al 0.8 v logic 0 = v al 0 . 8 v logic a1o = v ah 2.4 v logic 1 v ah 2.4 v x = don't care 12 dg509a_mil key v nc v+ d b s 1a s 4b s 1b s 4a nc d a nc nc s 2a a 1 s 2b gnd s 3a en s 3b a 0 91011 13 4 5 6 7 8 1 2 319 20 14 15 16 17 18 top view lcc decoders/drivers a 0 d a s 2b a 1 s 3a d b s 3b en s 4a s 4b dual-in-line and soic gnd v v+ s 1a s 1b s 2a decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg509a_mil

temp range package part number 55 125 c 16 - pin cerdip dg509aak 55 125 c 16 - pin cerdip dg509aak/883 55 to 125 c lcc-20 dg509aaz/883 16 - pin sidebraze jm38510/19008bea 16 - pin sidebraze jm38510/19008bec
a 1 a 0 en on switch x x 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 logic a0o = v al 0.8 v logic 0 = v al 0 . 8 v logic a1o = v ah 2.4 v logic 1 v ah 2.4 v x = don't care
dg508a_mil/509a_mil vishay siliconix document number: 70067 s-00405erev. c, 21-feb-00 www.vishay.com faxback 408-970-5600 5-3

voltage referenced to v v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v) 2 v to (v+) +2 v or . . . . . . . . . . . . . . . . . . . . . . . . 20 ma, whichever occurs first current (any terminal, except s or d) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current, s or d 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (k suffix) 65 to 150 c . . . . . . . . . . . . . . . . . . . (j and y suffix) 65 to 125 c . . . . . . . . . . . . . . power dissipation (package) b 16-pin cerdip c 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lcc-20 c 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x or in x exceeding v+ or v will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 12 mw/ c above 75 c. p sbl test conditions unless otherwise specified t b a suffix 55 to 125 c ui parameter symbol v+ = 15 v, v = 15 v v in = 2.4 v, 0.8 v f temp b min d typ c max d unit analog switch analog signal range e v analog full 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = 200 a room full 240 400 500 r ds(on) match r ds(on) 10 v < v s < 10 v room 6 % source off leakage current i s(off) v en = 0 v, v s = 10 v v d = 10 v room full 1 50 1 50 a drain off lk c t i d(off) v en = 0 v v d = 10 v dg508a_mil room full 10 200 10 200 a leakage current i d(off) v d = 10 v v s = 10 v dg509a_mil room full 10 100 10 100 na drain on lk c t i d(on) v s = v d = 10 v dg508a_mil room full 10 200 10 200 leakage current i d(on) v s = v d = 10 v dg509a_mil room full 10 100 10 100 digital control logic input current itvlt hih i ah v a = 2.4 v room full 10 30 0.002 a gp input voltage high i ah v a = 15 v room full 0.006 10 30 a logic input current input voltage low i al v en = 0 v, 2.4 v, v a = 0 v room full 10 30 0.002 dynamic characteristics transition time t trans see figure 2 room 0.6 1.0 break-before-make time t open see figure 4 room 0.2 s enable turn-on time t on(en) see figure 3 room 1 1.5 s enable turn-off time t off(en) see figure 3 room 0.4 1.0 charge injection q see figure 5 room 6 pc off isolation oirr v en = 0 v, r l = 1 k , c l = 15 pf v s = 7 v rms , f = 500 khz room 68 db logic input capacitance c in f = 1 mhz room 8 f source off capacitance c s(off) v en = 0 v, v s = 0 v, f = 140 khz room 6 pf drain off capacitance c d(off) v en = 0 v, v d = 0 v f 140 kh dg508a_mil room 25 pf drain of f capacitance c d(off) en , d f = 140 khz dg509a_mil room 12
dg508a_mil/509a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-4 document number: 70067 s-00405erev. c, 21-feb-00
p sbl test conditions unless otherwise specified t b a suffix 55 to 125 c ui parameter symbol v+ = 15 v, v = 15 v v in = 2.4 v, 0.8 v f temp b min d typ c max d unit power supplies positive supply current i+ v en = 0 v or 2.4 v room 1.3 2.4 ma negative supply current i v en = 0 v or 2 . 4 v room 1.5 0.7 ma notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. 500 20 10 0 10 20 400 300 200 100 0 2.5 2.0 1.5 1.0 0.5 0 input switching threshold vs. v+ and v supply voltages 500 16 15 15 10 5 0 5 10 15 14 12 10 8 6 4 2 0 450 400 350 300 250 200 150 100 50 0 10 5 0 5 10 15 r ds(on) vs. v d and power supply r ds(on) vs. v d and temperature charge injection vs. analog voltage (v s ) v+, v positive and negative supplies (v) v d drain voltage (v) o5 o10 o15 o20 v+ = 15 v v = 15 v v+ = 15 v v = 15 v (v) t v q (pc) 15 5 5 15 5 v 7.5 v 10 v 15 v 20 v 125 c 25 c 55 c r ds(on) drain-source on-resistance ( r ds(on) drain-source on-resistance ( v d drain voltage (v) v s source voltage (v) ) )
dg508a_mil/509a_mil vishay siliconix document number: 70067 s-00405erev. c, 21-feb-00 www.vishay.com faxback 408-970-5600 5-5
6 4 2 0 2 4 6 v+ = 15 v v = 15 v 100 k 10 k 1 m supply current vs. switching frequency i+, i (ma) i+ i 0 20 40 60 80 100 120 0 20 40 60 80 100 120 1400 55 1200 1000 800 600 400 200 35 15 5 25 45 65 105 125 85 1100 10 12 14 16 18 20 22 1000 900 800 700 600 500 400 300 200 1 k 1 m 10 m 10 k 100 k cerdip plastic v+ = 15 v v = 15 v ref. 0 dbm v+ = 15 v v = 15 v ref. 0 dbm 100 k 10 k 1 m 1 k 10 m off isolation vs. frequency crosstalk vs. frequency switching time vs. temperature switching time vs. positive supply voltage temperature ( c) isol (db) t trans , t open (ns) v+ = 15 v v = 15 v t trans t trans t open t open (db) talk x cerdip plastic v+ = 15 v v = 15 v v d = 14 v i d(on) , i d(off) i s(off) 100 na 10 na 1 na 100 pa 10 pa 55 35 15 5 25 45 65 85 105 125 , i s temperature ( c) leakages vs. temperature i d f frequency (hz) v+ positive supply (v) f frequency (hz) f frequency (hz) t trans , t open (ns)
dg508a_mil/509a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-6 document number: 70067 s-00405erev. c, 21-feb-00 25 51015 15 5 5 15 25 (pa) i s i s(off) vs. analog voltage i s(off) i d(on) , i d(off) vs. analog voltage (pa) i d 20 0 20 40 60 15 10 5 5 15 10 0 charge injection vs. power supply voltage 12 10 8 0 510 6 4 15 20 25 2 q (pf) 0 v+ = 15 v v = 15 v v s = v d t a = 25 c v+ = 15 v v = 15 v t a = 25 c i d(off) i d(on) v s source voltage (v) v+, v positive and negative supplies (v) v d drain voltage (v) 15 10 5 0
figure 1. v+ en v a x + v v+ a 0 decode/ drive s 1 s x d v+ v + v + v+ v+ v+ v+ v v gnd
dg508a_mil/509a_mil vishay siliconix document number: 70067 s-00405erev. c, 21-feb-00 www.vishay.com faxback 408-970-5600 5-7 figure 2. transition time a 1 a 0 a 2 a 1 a 0 +15 v 15 v en v+ v gnd d 35 pf v o s 1 s 2 s 7 s 8 50 300 10 v 10 v +15 v 15 v en v+ v gnd 35 pf v o s 1 s 1a s 4a , d a s 4b 50 300 10 v 10 v d b logic input switch output v s8 v o t trans t r <20 ns t f <20 ns s 8 on s 1 on t trans 0 v v s1 50% 90% 90% 3 v 0 v dg508a_mil dg509a_mil figure 3. enable switching time logic input switch output v o t r <20 ns t f <20 ns 3 v 0 v 0 v t off(en) t on(en) 50% 90% 10% en s 1 s 2 s 8 a 0 a 1 a 2 50 1 k v o v+ gnd v d 5 v 35 pf 15 v +15 v s 1b s 1a s 4a , d a s 2b s 4b d b en a 0 a 1 50 1 k v o v+ gnd v 5 v 35 pf 15 v +15 v dg508a_mil dg509a_mil
dg508a_mil/509a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-8 document number: 70067 s-00405erev. c, 21-feb-00 figure 4. break-before-make interval 50% 80% logic input switch output v o v s t open t r <20 ns t f <20 ns 0 v 3 v 0 v en v+ gnd v +5 v 35 pf 15 v +15 v +2.4 v a 2 d b , d all s and d a 300 v o 50 a 1 a 0 dg508a_mil dg509a_mil figure 5. charge injection a 0 en a 1 a 2 v o v+ gnd v d 15 v +15 v v g r g s x c l 10 nf channel select 3 v 0 v off on logic input switch output v o v o is the measured voltage due to charge transfer error q, when the channel turns off. q = c l x v o off figure 6. off isolation r l 1 k v o v+ gnd v 15 v +15 v a 2 d a 1 a 0 s 8 s x v s en r g = 50 off isolation = 20 log v out v in v in figure 7. crosstalk r l 1 k v o v+ gnd v 15 v +15 v a 2 d a 1 a 0 s 8 s x v s en r g = 50 crosstalk = 20 log v out v in v in s 1
dg508a_mil/509a_mil vishay siliconix document number: 70067 s-00405erev. c, 21-feb-00 www.vishay.com faxback 408-970-5600 5-9
figure 8. insertion loss figure 9. source drain capacitance r l 1 k a 2 v o d r g = 50 insertion loss = 20 log v out a 1 v in a 0 v s s 1 v+ gnd v 15 v +15 v en f = 1 mhz s 1 d en +15 v 15 v gnd v+ v meter hp4192a impedance analyzer or equivalent s 8 a 1 a 2 a 0 channel select v+ positive supply voltage (v) v negative supply voltage (v) v in logic input voltage v inh(min) /v inl(max) (v) v s or v d analog voltage range (v) 15 10 12 8 b 15 12 10 8 2.4/0.8 2.4/0.8 2.4/0.6 2.4/0.4 15 to 15 12 to 12 10 to 10 8 to 8 notes: a. application hints are for design aid only, not guaranteed and not subject to production testing. b. operation below 8 v is not recommended. overvoltage protection a very convenient form of overvoltage protection consists of adding two small signal diodes (1n4148, 1n914 type) in series with the supply pins (see figure 11). this arrangement effectively blocks the flow of reverse currents. it also floats the supply pin above or below the normal v+ or v value. in this case the overvoltage signal actually becomes the power supply of the ic. from the point of view of the chip, nothing has changed, as long as the difference between v s and the v rail doesn't exceed +44 v. the addition of these diodes will reduce the analog signal range to 1 v below v+ and 1 v above v, but it preserves the low channel resistance and low leakage characteristics. 1n4148 dg508a_mil d 15 v 1n4148 v+ v v g v v s x v g v+ v +15 v figure 10. overvoltage protection using blocking diodes internal junction internal junction
dg508a_mil/509a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-10 document number: 70067 s-00405erev. c, 21-feb-00 (multiplexer on-off control) analog inputs (outputs) clock in nc enable in analog output (input) dg508a_mil d en dm7493 +15 v gnd +5 v analog inputs (outputs) analog output (input) +15 v 15 v dg509a_mil en gnd v+ v differential differential clock in nc enable q gnd +5 v nc q reset j k clk j k clk clear clear 1/2 mm74c73 1/2 mm74c73 s 1 s 8 a 0 a 1 a 2 q b q c q d q a r 01 r 02 s 1a s 4a s 1b s 4b d a d b a 0 a 1 q q figure 11. 8-channel sequential multiplexer/ demultiplexer figure 12. differential 4-channel sequential multiplexer/ demultiplexer +15 v 15 v gnd v+ v

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